1. Field of the Invention
This invention pertains generally to field-programmable logic arrays, and more particularly to circuits and methods for reducing power consumption using multiple supplies.
2. Description of Related Art
Field Programmable Gate Arrays (FPGAs) are an important and commonly used circuit element in conventional electronic systems. FPGAs are attractive for use in many designs in view of its low non-recurring engineering costs (NRE) and rapid time to market. FPGA circuitry is also being increasingly integrated within other circuitry to provide a desired amount of programmable logic.
Many applications can be implemented using FPGA devices without the need of fabricating a custom integrated circuit, or application specific integrated circuit (ASIC) as it is called. Although ASICs allow all the circuitry to be customized to the application, including all transistor parameters, routing and so forth, they are very costly in terms of engineering costs, mask fabrication, and minimum order sizes. ASICS have been designed with more than one supply which is readily implemented in the masking which is developed around that specific application circuit. In ASICs the geometries of all elements can be customized for the specific application. In some ASIC designs different level converter circuits have been used with two supply designs. DCVS level converters and level converters with data latch have been proposed in for use in ASIC design. These level converters use both high and low supply voltage levels for a single rail and create extra constraints for power/ground routing.
However, it should be appreciated that the fixed patterns implemented within FPGAs provide a number of challenges which have prevented multi source techniques from providing real world benefits.
Typically, an FPGA is made up of two types of blocks: logic blocks (typically comprising look-up tables (LUTs)), and interconnects (routing). More complicated FPGAs may also include blocks of dedicated RAM and some common logical blocks such as adders, multipliers, and so forth.
FIG. 1 depicts a conventional 4-input LUT using single Vdd and Vt and is referred to herein as a “LUT_SVST”. LUTs are utilized as a gate that can be programmed for any desired logic function. A single bit output LUT with a desired number of input terms is usually implemented as a storage block of memory cells with a one-bit word. To program the LUT, the truth table of the gate being implemented by the LUT is loaded into the storage block, with the truth table corresponding to the address lines of the storage element, and the output of the truth table being the stored value at that address. The storage element may be directly connected to the output, coupled to other elements or interconnects, a flip-flop inserted between the gate and the output for clocked logic, and so forth.
The inputs and outputs to the various LUTs are connected to each other by interconnects, such as including routing blocks (e.g., including wire segments, connection blocks, and switch blocks). Each routing block has several wires connected to it, and these wires have programmable connections between them. Since the total number of possible connections increases rapidly in response to the number of wires connected to the routing block, most routing blocks are designed with a limited number of paths through the block. The LUTs and interconnects are usually distributed throughout the FPGA, such as giving it a regular array structure.
One of the drawbacks of FPGA circuitry is a low power efficiency which limits applicability of the devices. Attention has been increasingly focused on improving FPGA power efficiency, as power has become an increasingly important design constraint. One study introduced hierarchical interconnects to reduce interconnect power, but they do not consider deep sub-micron effects such as the increasingly large leakage power. Another study developed a flexible power evaluation framework referred to as “fpga EVA-LP” (fpga_EVALP) and performed dynamic and leakage power evaluation for FPGAs with cluster-based logic blocks and island style routing structure.
Accordingly, it will be appreciated that interconnect power consumption is a major detractor to the use of FPGAs. The present invention reduces interconnect power levels without significantly increasing circuit cost or complexity.